Many modern electronic devices, such as, for example, computer processors, chips, and circuits, often employ a high frequency signal to provide a clock signal. However, there are some applications where flexibility in the clock frequency is desired, without requiring extensive additional hardware. Recent developments in electronic devices include circuits that can divide down high-frequency clocks in a controlled manner, which can provide desired flexibility in clock frequency, such that the fluctuation in signal current over time, di/dt, associated with the division is minimized. One skilled in the art will understand that by minimizing di/dt, power supply integrity can be improved, and that power supply integrity is increasingly important as supply voltages are scaled down.
In one such recently-developed circuit, generally, a shift register loads a set of code patterns for high-frequency clock-masking in a parallel manner. Once the loading process is complete, the shift register shifts into a serial mode and runs the patterns in a round-robin manner. One skilled in the art will understand that in a serial (round-robin) configuration, the last bit in the shift register shifts to the first bit-position, instead of or in addition to shifting out of the shift register. A system can then use the output of the shift register to mask out specific pulses of the high-frequency clock, thereby achieving the desired frequency division.
For example, an end-use system, such as, for example, a processor and/or circuit that uses a clock signal at a lower frequency than the provided high-frequency clock signal can employ the shift register output to mask the high-frequency clock. Additionally, an intermediate-use system, such as, for example, a processor and/or circuit that, in part, provides a clock signal at a lower frequency than the high-frequency clock signal to other systems and/or components, can also employ the shift register output to mask the high-frequency clock. One skilled in the art will understand that other configurations can also be employed.
For further illustration, FIG. 1 depicts a representation 100 of a general implementation of two bits of a shift register configured to operate in parallel mode and serial (round-robin) mode. As illustrated, the block labeled “Control n” 105 receives two control inputs. One control input is a clock signal (CLK) 110 and the other control input is a control signal (Parallel/Serial select 115) that indicates whether the system is to operate in serial (round-robin) mode or parallel mode. The “Control n” block 105 receives the two control inputs 110 and 115, and, in a synchronous manner, enables/disables the parallel and serial paths of the shift register, as will be understood to one skilled in the art. More particularly, Parallel/Serial select signal 115 determines whether certain gates will be open or closed, by controlling serial select signal 120 and parallel select signal 125. Serial select signal 120 controls gate 122 and parallel select signal 125 controls gate 127.
During the transitions between parallel and serial modes, if the clock frequency is high, an indeterminate state can latch on to the flip-flops (FFs)/latches of “bit n” 130 in the shift register 135. For example, during the parallel mode of operation, “Control n” block 105 selects the path indicated by arrow “A” 140 in FIG. 1 and disables the path indicated by arrow “B” 145, as one skilled in the art will understand. Similarly, when “Control n” block 105 disables the parallel mode and enables the serial mode, “Control n” block 105 disables path “A” 140 and enables path “B” 145.
During this transition period, shifting from serial input from “Node 2” 155 to parallel input from parallel input bit n 160, “Node 1” 150, the input to “bit n” 130 of the shift register 135, can be in a state that is not well defined. In particular, CLK 110 keeps the input FF/latch of “bit n” 130 open for a maximum time equal to T/2, where T is the period of CLK 110. Assuming that it takes Tb time for a signal from “Node 2” 155 in FIG. 1 to arrive at “Node 1” 150, the probability that the not-well-defined state at “Node 1” 150 will latch onto “bit n” 130 of shift register 135 increases as the magnitudes of Tb and T/2 become comparable.
Thus, as Tb and T/2 become comparable, particularly at high clock frequencies, a not-well-defined state at “Node 1” 150 can occur. Therefore, in systems that use the shift register 135 output to mask phase locked loop (PLL) clock signals to generate lower frequency clocks, it is important to be able to verify the contents of the shift register 135 over time. In practice, this verification typically includes loading the parallel bits and observing the serial (round-robin) output of the shift register 135 at full speed to ensure the shift register 135 contains the desired code.
Generally, there are two typical options to test such a circuit at full speed in a manufacturing/lab environment. In one case, a test engineer, for example, can construct a laboratory setup that has a very high bandwidth (>5 GHz) and, therefore, is capable of directly monitoring the output of the di/dt reducing circuit, that is, the serial (round-robin) output of the shift register. However, a lab setup with sufficient bandwidth to characterize the system running at full speed at very high frequencies can be very expensive to maintain and therefore can be cost prohibitive in many environments.
In another case, a test engineer, for example, can employ a series of serial registers to store the data from the outputs. However, this approach can require the introduction of a large number of on-chip serial registers. For example, there can be thousands of cycles of system output to store, requiring a large hardware increase. Similarly, the number of serial shift registers available limits the number of cycles that can be observed. Generally, if the system has “n” bits and it is desirable to observe “y” cycles, the serial shift register will need at least yXn latches. Thus, for example, for an n-bit di/dt reducing circuit, 10Xn serial shift registers are necessary to observe 10 cycles of the circuit. Introducing many additional shift registers can consume a large area as well as a significant amount of power.
Therefore, there is a need for a system and/or method for examining high-frequency clock-masking signal patterns at full speed that addresses at least some of the problems and disadvantages associated with conventional systems and methods.